Non-volatile memory devices which store electrons in nano-crystals instead of floating gates, are presently of great interest, due to potential advantages in memory cell size and power dissipation, compared to memory technologies currently in use. The use of nano-crystals for electron storage will provide greater reliability and low-voltage operation. Research in this area is reported in the article “Volatile and Non-Volatile Memories in Silicon with Nano-Crystal Storage” by Tiwari et al., IEEE, IEDM, 1995, pgs. 521-524, the disclosure of which is incorporated herein by reference.
FIG. 1 is a sectional view illustrating a floating-gate n-channel MOS electron memory device. In the figure, reference numeral 1 denotes a silicon (Si) substrate, reference numeral 2 a tunnel gate oxide layer, reference numeral 4 a control gate oxide layer, reference numeral 5 a control gate electrode, reference numeral 6 a source region, reference numeral 7 a drain region, reference numeral 8 an inversion layer, and reference numeral 3 silicon nano-crystals. This device is characterized in that silicon nano-crystals 3 with a dimension, for example, of less than about 5 nm are provided between a tunnel oxide of 1.5 nm (or less) and control oxide of 7 nm or less. If alternate high dielectric constant dielectrics are employed, the physical film thickness can be greater, as the “effective” thickness will be less due to the higher dielectric constant of the dielectric material. A high dielectric constant dielectric is one which has a dielectric constant greater than silicon dioxide.
During programming of the device, electrons contained in the inversion layer 8 tunnel into the silicon nano-crystals 3 on the tunnel oxide layer 2 when the gate is forward biased with respect to the source and drain. The resulting stored charge in the silicon nano-crystals 3 effectively shifts the threshold voltage of the device to a more positive potential as the control gate now has to overcome the effects of this change. The gate can also be programmed by a hot electron technique typically used in flash memory. The state of electrons in the silicon nano-crystals 3 can be sensed by sensing a change in the current flowing through the inversion layer 8 with respect to the gate voltage.
FIGS. 2A, 2B and 2C are views illustrating changes in the conduction band of the above-described device. When a positive voltage has been applied to the gate with respect to the source and drain regions, an electron is transmitted and accumulated into the silicon nano-crystals 3 from the inversion layer 8 via the tunnel oxide layer 2, as is shown in FIG. 2A (“Write” state). Even if the application of the voltage to the gate electrode 5 is removed, the electron is retained in the silicon nano-crystals 3, as is shown in FIG. 2B (“Store” state). The stored electron increases the threshold voltage of the transistor as it screens the control gate voltage. On the other hand, when a negative voltage has been applied to the gate with respect to the source and drain regions, the electron accumulated in the silicon nano-crystals is discharged to the substrate side via the tunnel oxide layer 2, as is shown in FIG. 2C. In this state, the threshold voltage returns to its original value (“Erase” state).
As described above, an electron can be transmitted into, retained in, and discharged from the silicon nano-crystals 3, and the threshold voltage of the device varies depending upon whether or not electrons are accumulated in the silicon nano-crystals 3. Hence, this device can be used as a memory device.
In the conventional floating-gate device using the stored electron phenomenon, a low dielectric constant dielectric, such as SiO2 is used as a gate oxide layer. The SiO2 gate oxide has a dielectric constant of 3.9 which does not allow scaling and also does not permit low voltage operation. Also, depending on what control gate oxide is used and subsequent processing steps used, the silicon nano-crystals could oxidize, which would impede or destroy memory device operation. For example, if a high constant (high-K) dielectric, such as Ta2O5, is used as the control gate oxide to scale the gate threshold voltage for low voltage application, formation of the Ta2O5 control gate oxide could oxidize the silicon nano-crystals destroying the memory cell. The present invention enables integration of high constant dielectrics, which in turn allows for reduction of operating voltages.